The invention relates to technology for designing and verifying an integrated circuit (“IC”) design.
With the rapid growth of the wireless and portable electronic markets, there is a constant demand for new technological advancements. This has resulted in more and more functionality being incorporated into battery-operated products, increasing challenges for power management of such devices. Such challenges include minimization of leakage power dissipation, designing efficient packaging and cooling systems for power-hungry IC's, or verification of functionality or power shut-off sequences early in the design. These challenges are expected to become even more difficult with the continuous shrinking of process nodes using today's CMOS technology. Managing design and verification for power will be as critical, if not more than, for timing and area in today's IC design flow for portable consumer electronics.
Modern electronic design is typically performed with computer aided design (CAD) tools or electronic design automation (EDA) systems. To design an integrated circuit, a designer first creates high level behavior descriptions of the IC device using a high-level hardware design language (HDL). Common examples of HDLs include Verilog and VHDL. An EDA system typically receives the high level behavior descriptions of the IC device and translates this high-level design language into netlists of various levels of abstraction. Essentially, the process to implement an electronic device begins with functional design and verification (e.g., using RTL), and then proceeds to physical design and verification.
Older technologies for power optimization and implementation techniques are only leveraged at the physical implementation phase of the design. Certain advanced power management techniques like multiple power domains with power shut-off (PSO) methodology can only be implemented at the physical level (i.e., post synthesis). These advanced power management design techniques significantly change the design intent, yet none of the intended behavior can be captured in the RTL. This creates a large gap in the RTL to GDSII implementation and verification flow where the original RTL is no longer reliable and cannot be used to verify the final netlist implementation containing the advanced power management techniques. In addition, these specialized power management techniques at the physical implementation stage cannot be used by EDA tools at other stages of the design process, and therefore cannot be used by EDA tools at an earlier RTL or gate level stage of the IC design process to perform, for example, functional verification. One reason this is important is because verification of low power designs only at the physical implementation stage of the design process may not capture all potential design flaws within the IC, particularly sequence-related problems for power modes that are ideally tested at the functional stage of the IC design process.
As a result, there is a growing demand from designers to model and optimize the power requirements of a design to help build highly power efficient designs. This has given rise to a variety of low-power techniques that designers can employ on their designs to achieve their power goals.
Recently, techniques have been introduced that allow designers to define their power intents across various design phases. In particular, common power file formats have been introduced which is capable of capturing power-related design intent information, power-related power constraints, and power-related technology information for an integrated circuit. Examples of such common file formats include the Common Power Format (CPF) and the Unified Power Format (UPF). The same power information file is supported by the EDA tools across all the design phases, such as simulation, synthesis, and routing. This allows various design levels to communicate their power intents with each other without having any risk of losing information, e.g., due to file translations. Since all the design teams talk the same power language, this helps to get a common focus on the overall power goals of the design.
The drawback to these approaches is that for simulation, the conventional approaches to implementing common power file formats have focused only on the digital aspects of the design. This causes problems when the designers wish to configure designs to use analog abstractions as well as digital abstractions to gain better accuracy on the blocks and perform analog-mixed-signal (AMS) simulation. The analog blocks require continuous time-domain (analog) simulators to computer their behavior while digital blocks rely on discrete time event driven (digital) simulators. A mixed-signal simulator uses both analog and digital simulation paradigms and performs the required inter-domain communication to simulate the interaction between analog and digital blocks. Such inter-domain communication is a very important component for controlling the accuracy and performance of the mixed-signal simulation. With the ever increasing complexities of System-On-A-Chip designs, mixed-signal simulation has become a very critical aspect of design verification process. The inability to adequately perform such simulation for low power applications is a severe detriment to the modern design process.
Therefore, there is a need for an improved approach for verifying and simulating mixed signal electronic circuits with specialized power requirements, such as low power designs.